ZL10PLD - Revision history

Grzegorzbecker at 10:14, 2 November 2024

2024-11-02T10:14:22Z

← Older revision		Revision as of 10:14, 2 November 2024
Line 1:		Line 1:
	~~__jzXpdf__~~		__jzpdf__
	===== Description =====		====== Description ======
	The dipPLD modules are designed to helps using of Spartan 3 FPGA devices by people that can’t use automatic assembly of QFP packages.		The dipPLD modules are designed to helps using of Spartan 3 FPGA devices by people that can’t use automatic assembly of QFP packages.

Admin: Text replacement - "jzpdf" to "jzXpdf"

2024-10-30T00:53:16Z

Text replacement - "__jzpdf__" to "__jzXpdf__"

← Older revision		Revision as of 00:53, 30 October 2024
Line 1:		Line 1:
	~~__jzpdf__~~		__jzXpdf__
	===== Description =====		===== Description =====
	The dipPLD modules are designed to helps using of Spartan 3 FPGA devices by people that can’t use automatic assembly of QFP packages.		The dipPLD modules are designed to helps using of Spartan 3 FPGA devices by people that can’t use automatic assembly of QFP packages.

Anna Kubacka at 09:15, 24 September 2020

2020-09-24T09:15:57Z

← Older revision		Revision as of 09:15, 24 September 2020
Line 6:		Line 6:
	[[File:zl10pld.jpg\|none\|400px\|thumb\|center]]		[[File:zl10pld.jpg\|none\|400px\|thumb\|center]]
	</center>		</center>

	===== Key features =====		===== Key features =====
	* XC3S200 Spartan 3 FPGA device in VQFP100 package (equivalent for 200000 logic gates, 12 hardware multipliers, 4 frequency multipliers, 216kb of Block SRAM)		* XC3S200 Spartan 3 FPGA device in VQFP100 package (equivalent for 200000 logic gates, 12 hardware multipliers, 4 frequency multipliers, 216kb of Block SRAM)

Admin at 08:45, 30 August 2018

2018-08-30T08:45:49Z

← Older revision		Revision as of 08:45, 30 August 2018
Line 23:		Line 23:
	{\| class="frame-green"		{\| class="frame-green"
	\|-		\|-
	\| For ZL10PLD dipPLD module are available free PCB and SCH libraries for Protel99SE and Protel DXP. They can be downloaded from: ~~http~~://~~www~~.kamami.pl/~~dl/~~zl10pld_libs.zip		\| For ZL10PLD dipPLD module are available free PCB and SCH libraries for Protel99SE and Protel DXP. They can be downloaded from: https://download.kamami.pl/p29367-zl10pld_libs.zip
	\|}		\|}

Admin: Text replacement - "jzXpdf" to "jzpdf"

2018-08-10T07:17:15Z

Text replacement - "__jzXpdf__" to "__jzpdf__"

← Older revision		Revision as of 07:17, 10 August 2018
Line 1:		Line 1:
	~~__jzXpdf__~~		__jzpdf__
	===== Description =====		===== Description =====
	The dipPLD modules are designed to helps using of Spartan 3 FPGA devices by people that can’t use automatic assembly of QFP packages.		The dipPLD modules are designed to helps using of Spartan 3 FPGA devices by people that can’t use automatic assembly of QFP packages.

Admin: Text replacement - "jzpdf" to "jzXpdf"

2018-08-10T07:16:34Z

Text replacement - "__jzpdf__" to "__jzXpdf__"

← Older revision		Revision as of 07:16, 10 August 2018
Line 1:		Line 1:
	~~__jzpdf__~~		__jzXpdf__
	===== Description =====		===== Description =====
	The dipPLD modules are designed to helps using of Spartan 3 FPGA devices by people that can’t use automatic assembly of QFP packages.		The dipPLD modules are designed to helps using of Spartan 3 FPGA devices by people that can’t use automatic assembly of QFP packages.

Wlodzimierzhepner: /* Key features */

2018-07-30T11:08:35Z

Key features

← Older revision		Revision as of 11:08, 30 July 2018
Line 8:		Line 8:

	===== Key features =====		===== Key features =====
	* XC3S200 Spartan 3 FPGA device in VQFP100 package (equivalent for 200000 logic gates, 12 hardware ~~mul- tipliers~~, 4 frequency multipliers, 216kb of Block SRAM)		* XC3S200 Spartan 3 FPGA device in VQFP100 package (equivalent for 200000 logic gates, 12 hardware multipliers, 4 frequency multipliers, 216kb of Block SRAM)
	* flash configuration memory size: 1Mb (XCF01S)		* flash configuration memory size: 1Mb (XCF01S)
	* 61 I/O lines (including five 5V-tolerant input lines)		* 61 I/O lines (including five 5V-tolerant input lines)
Line 33:		Line 33:
	</center>		</center>
	\|}		\|}


	===== Standard equipment =====		===== Standard equipment =====

Anna Kubacka: Created page with "jzpdf ===== Description ===== The dipPLD modules are designed to helps using of Spartan 3 FPGA devices by people that can’t use automatic assembly of QFP packages.
2018-07-13T09:41:28Z

Created page with "jzpdf ===== Description ===== The dipPLD modules are designed to helps using of Spartan 3 FPGA devices by people that can’t use automatic assembly of QFP packages. <cen..."

New page
jzpdf
===== Description =====
The dipPLD modules are designed to helps using of Spartan 3 FPGA devices by people that can’t use automatic assembly of QFP packages.

<center>
[[File:zl10pld.jpg|none|400px|thumb|center]]
</center>

===== Key features =====
* XC3S200 Spartan 3 FPGA device in VQFP100 package (equivalent for 200000 logic gates, 12 hardware mul- tipliers, 4 frequency multipliers, 216kb of Block SRAM)
* flash configuration memory size: 1Mb (XCF01S)
* 61 I/O lines (including five 5V-tolerant input lines)
* built-in LVC/LCX inverters for buffering 6 I/O lines
* switch for manual configuring FPGA
* LED indicating correctly configured FPGA
* JTAG interface (ZL11PRG, ZL11PRG-M or ZL4PRG)
* quartz generator 3.6864 MHz
* built-in voltage regulators: 1.2/2.5 and 3.3V
* 4.4–7VDC power supply
* current consumption: 110mA (depend on frequency)
* ready to use with ZL9PLD base board

{| class="frame-green"
|-
| For ZL10PLD dipPLD module are available free PCB and SCH libraries for Protel99SE and Protel DXP. They can be downloaded from: http://www.kamami.pl/dl/zl10pld_libs.zip
|}

{| class="frame-green"
|-
| ZL10PLD module works with ZL9PLD base board. <center>
[[File:zl9pld.jpg|none|400px|thumb|center]]
</center>
|}

===== Standard equipment =====

<center>
{| class="wikitable" style="width: 1000px;"
|-
! style="text-align: center;"|Code
! style="text-align: center;"|Description
|-
| style="text-align: center;"|<b>ZL10PLD</b>
| style="text-align: left;"|
* Assembled module with XC3S200-VQG100 device
|}
</center>

===== Module configuration =====
Electrical schematic of ZL10PLD is shown in the below picture.

<center>
[[File:ZL10PLD_schemat-kopia.png|none|900px|thumb|center]]
</center>

===== Arrangement of the most important module =====

<center>
[[File:ZL10PLD_pcb.png|none|800px|thumb|center]]
</center>

===== Module pins =====

<center>
[[File:ZL10PLD_io.png|none|400px|thumb|center]]
</center>

{| class="frame-green"
|-
| I/O line, marked by „p36” symbol, is an input of clock signal (turned in the stage of quartz generator which is installed on ZL10PLD ). It can be used only as an output to the cooperation with devices which are powered by 3.3V voltage.
|}

{| class="frame-green"
|-
| I/O line of ZL10PLD are compatible only with 3.3V logic! It does not concern five selected lines which are equipped with voltage buffers LVC/LCX.
|}

===== JTAG connector =====
ZL10PLD module is equipped with IDC connector, for connecting ISP programmer (for example: ZL11PRG, ZL11PRG-M, ZL4PRG). Placement of this connector on the board and signals arrangement are shown in the below pictures.

<center>
[[File:ZL10PLD_jtag_loc.png|none|400px|thumb|center]]
</center>

<center>
[[File:ZL10PLD_jtag_sygnaly-kopia.png|none|400px|thumb|center]]
</center>

FPGA device and configuration memory (Flash memory U2) are connected to a JTAG chain, as in the below picture. This connection enables independent Flash memory programming and configuring of FPGA device with the use of programmer which is in accordance with Xilinx DLC III programmer (for example: ZL11PRG, ZL4PRG).

<center>
[[File:ZL10PLD_jtag.png|none|400px|thumb|center]]
</center>

===== FPGA configuration mode selection =====
FPGA device, after turning on voltage, can be automatically configured (configuration is copied from Flash configuration memory) or can wait for configuration data which are supplied by the user with the use of JTAG interface. The choice of configuration mode takes place with the use of JP4 connector, according to the description, placed on the printed board.

<center>
[[File:ZL10PLD_jump.png|none|400px|thumb|center]]
</center>

===== FPGA manual reconfiguration switch =====
With the use of placed on the board button (its placement is shown in the below picture) the user in any moment can restore FPGA configuration which is saved in the memory. The correct FPGA configuration is indicated by RDY LED.

<center>
[[File:ZL10PLD_key.png|none|400px|thumb|center]]
</center>

===== Quartz generator =====
ZL10 PLD is equipped with quartz generator with 3.6864MHz output frequency and 5V power supply voltage. Thanks owing to the fact that the quartz generator is placed in the socket, the user can exchange it for any other, useful in application testing.

<center>
[[File:ZL10PLD_gen.png|none|400px|thumb|center]]
</center>

===== ZL9PLD base board peripherals connection =====
The ZL10PLD module is adapted to cooperation with ZL9PLD base board. On picture below is shown way of connection to module peripherals from ZL9PLD base board.

<center>
[[File:ZL10PLD_peryferia.png|none|800px|thumb|center]]
</center>

ZL10PLD - Revision history

Grzegorzbecker at 10:14, 2 November 2024

Admin: Text replacement - "__jzpdf__" to "__jzXpdf__"

Anna Kubacka at 09:15, 24 September 2020

Admin at 08:45, 30 August 2018

Admin: Text replacement - "__jzXpdf__" to "__jzpdf__"

Admin: Text replacement - "__jzpdf__" to "__jzXpdf__"

Wlodzimierzhepner: /* Key features */

Admin: Text replacement - "jzpdf" to "jzXpdf"

Admin: Text replacement - "jzXpdf" to "jzpdf"

Admin: Text replacement - "jzpdf" to "jzXpdf"